Antonio Miele is an assistant professor at the Department of Electronics, Information and Bioengineering (DEIB), Politecnico di Milano, Milano, Italy (according to the Italian Law n. 240/2010 - art. 24, par. 3, letter B). He received his Ph.D. in Information Technology in 2010 from the same institution where he worked as postdoc research assistant from 2010 to 2014. During his doctoral studies he spent a 4-month period at European Space Agency - ESTEC in Nordwjik, Netherlands. Previously, he received the M.Sc. and the B.Sc. in Computer Science Engineering from Politecnico di Milano in 2006 and in 2003 respectively. In 2006 he also got the M.Sc. in Computer Science at the University of Illinois at Chicago, USA.
His main research interests are related to the definition of design and analysis methodologies for embedded computing systems, in particular focusing on fault tolerance and reliability issues, runtime resource management in heterogeneous multi-/many-core systems and FPGA-based systems design.
Dr. Miele is co-author of more than 70 scientific publications in international conference proceedings and selected journals. He has served as Program Chair the International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) in 2016 and in 2017; moreover, he is the "Adaptive and Learning Systems" DATE A6 Topic Chair from 2018 to 2021. Dr. Miele has served as Guest co-Editor two special sessions both focusing on fault tolerance in digital systems, one in the IEEE Transactions in Emerging Topics in Computing (2016-2017 and published in 2020), and one in the IET Computers & Digital Techniques (2017-2018, published in 2019). Finally, he is part of the technical program committees of various conferences, such as DATE, DFT, FPL, IOLTS, ARC, DSD.
Dr. Miele actively participated in various national and EU funded project: "SAVE" FP7 STREP project (2013-2016), "SMECY" EU-ARTEMIS project (2010-2013), "SCALOPES" EU-ARTEMIS project (2009-2010) and a MIUR-PRIN 2008 project (2010-2012). Finally, current activities on the definition of novel hardening strategies for image processing and machine learning applications are partially supported by an Intel Corporation research grant.

Download the complete curriculum vitae in PDF format here.

International Journals

• A.M. Hosseini Monazzah, A.M. Rahmani, A. MIELE, N. Dutt:, CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of Approximation, In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Online early access since April 2020.


• G. Tanganelli, L. Cassano, A. MIELE, C. Vallati: A methodology for the design and deployment of distributed cyber-physical systems for smart environments, In Future Generation Computer Systems, Elsevier, Vol. 109, pp. 420–430, August 2020.


• M. Biasielli, C. Bolchini, L. Cassano, E. Koyuncu. A. MIELE: Neural Network Based Fault Management Scheme for Reliable Image Processing, In IEEE Transactions on Computers, Vol. 69, no. 5, pp. 764–776, May 2020.


• A. MIELE, A. Kanduri, K. Moazzemi, D. Juhasz, A.M. Rahmani, N.D. Dutt, P. Liljeberg, A. Jantsch: On-Chip Dynamic Resource Management, In Foundations and Trends in Electronic Design Automation, Now Publisher, Vol. 13, no. 1-2, pp. 1-144, July 2019.


• D. Cerotti, A. MIELE, M. Gribaudo, A. Bobbio, C. Bolchini: Scalable analytical model for reliability measures in aging VLSI by interacting Markovian agents. In Performance Evaluation, Elsevier, Vol. 132, pp 21-37, August 2019.


• C. Bolchini, S. Cherubin, G.C. Durelli, S. Libutti, A. MIELE, M.D. Santambrogio: A Runtime Controller for OpenCL Applications on Heterogeneous System Architectures. In ACM SIGBED Reviews, Vol. 15, no. 1, pp. 29-35, February 2018.


• M. Haghbayan, A. MIELE, A.M. Rahmani, P. Liljeberg, H. Tenhunen: Performance/Reliability-aware Resource Management for Many-Cores in Dark Silicon Era. In IEEE Transactions on Computers, Vol. 66, no. 9, pp. 1599-1612, September 2017.


• M. Haghbayan, A. MIELE, A.M. Rahmani, P. Liljeberg, A. Jantsch, C. Bolchini, H. Tenhunen: Can Dark Silicon Be Exploited to Prolong System Lifetime? In IEEE Design & Test, Issue 2, pp. 51-59, April 2017.


• A.M. Rahmani, M. Haghbayan, A. MIELE, P. Liljeberg, A. Janthsch, H. Tenhunen: Reliability-Aware Runtime Power Management for Many-Core Systems the in Dark Silicon Era. In IEEE Transactions on VLSI Systems, Vol. 25, no. 2, pp. 427-440, February 2017.


• M. Rabozzi, G.C. Durelli, A. MIELE, J. Lillis, M.D. Santambrogio: Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation. In IEEE Transactions on VLSI Systems, Vol. 25, no. 1, pp. 151-165, January 2017.


• M. Haghbayan, A.M. Rahmani, A. MIELE, M. Fattah, J. Plosila, P. Liljeberg, H. Tenhunen: A Power-Aware Approach for Online Test Scheduling in Many-core Architectures. In IEEE Transactions on Computers, Vol. 65, no. 3, pp. 730-743, March 2016.


• A. MIELE: A fault-injection methodology for the system-level dependability analysis of multiprocessor embedded systems. In Journal of Microprocessors and Microsystems - Embedded Hardware Design, Elsevier, Vol. 38, No. 6, pp. 567-580, August 2014.


• C. Bolchini, A. MIELE, C. Sandionigi: Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms. In Journal of Electronic Testing: Theory and Applications, Springer, Vol. 29, no. 6, (2013), pp. 779-793.


• C. Bolchini, A. MIELE: Reliability-driven System-level Synthesis for Mixed-Critical Embedded Systems. In IEEE Transactions on Computers, Vol. 62, No. 12, pp. 2489-2502, December 2013.


• A. MIELE, C. Pilato, D. Sciuto: A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs. In International Journal of Embedded and Real-Time Communication Systems, IGI Global, Vol. 4, no. 1, pp 22-41, January-March 2013.


• C. Bolchini, M. Carminati, A. MIELE: Self-Adaptive Fault Tolerance in Multi-/Many-Core Systems. In Journal of Electronic Testing: Theory and Applications, Springer, Vol. 29, no. 2, (2013), pp. 159-175.


• A. MIELE, E. Quintarelli, E. Rabosio, L. Tanca: A data-mining approach to preference-based data ranking founded on contextual information. In Information Systems 38 (2013), pp. 524-544, June 2013.


• C. Bolchini, A. MIELE, C. Sandionigi: A novel design methodology for implementing reliability-aware systems on SRAM-based FPGAs. In IEEE Transactions on Computers, Vol. 60, No. 12, pp. 1744-1758, December 2011.


• C. Bolchini, A. MIELE, M. Rebaudengo, F. Salice, D. Sciuto, L. Sterpone, M. Violante: Software and Hardware Techniques for SEU Detection in IP Processors. In Journal of Electronic Testing: Theory and Applications, Springer, Vol. 24, no. 1-3, (2008), pp. 35-44.

Book Chapters

• A.M. Hosseini Monazzah, A.M. Rahmani, A. MIELE, N. Dutt: Exploiting Memory Resilience for Emerging Technologies: An Energy-aware Resilience Exemplar for STT-RAM Memories. in "Dependable Embedded Systems", to appear, Springer, 2020.


• C. Bolchini, M.K. Michael, A. MIELE, S. Neophytou: Dependability Threats. in M. Ottavi, D. Gizopoulos, and S. Pontarelli (eds.) "Dependable Multicore Architectures at Nanoscale", pp. 37-92, Springer, 2018 (ISBN: 978-3-319-54421-2).


• M.H. Haghbayan, A.M. Rahmani, A. MIELE, P. Liljeberg and H. Tenhunen: Online Software-Based Self-Testing in the Dark Silicon Era. in A.M. Rahmani, P. Liljeberg, A. Hemani, A. Jantsch, and H. Tenhunen (eds.) "The Dark Side of Silicon - Energy Efficient Computing in the Dark Silicon Era", pp. 259-287, Springer, 2017 (ISBN: 978-3-319-31596-6).


• V. Rana, F. Bruschi, A. MIELE, M.D. Santambrogio and D. Sciuto: Design Methodologies for Reconfigurable NoC-Based Embedded Systems. in Pierre-Emmanuel Gaillardon (eds.) "Reconfigurable Logic: Architecture, Tools, and Applications", pp. 185-213, CRC Press, 2015 (ISBN: 978-1-4822-6218-6).


• G. Agosta, M. Cartron, A. MIELE: Fault Tolerance. in M. Torquati, K. Bertels, S. Karlsson, F. Pacull (eds.) "Smart Multicore Embedded Systems", pp. 79-99, Springer, 2014 (ISBN: 978-1-4614-8799-9).

Editorial Contributions

• A. MIELE, M. Trefzer and S. Khursheed: Guest Editorial: Defect and Fault Tolerance in VLSI and Nanotechnology Systems, In IET Computers & Digital Techniques, Vol. 13, Issue 3, pp. 127-128, 2019.


• R. Shafik, Q. Yu, S. Khursheed, A. MIELE: Welcome Message of the Proceedings of 2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) , 2017, pp. iii.


• O. Khan, M.K. Michael, A. MIELE, Q. Yu: Foreword of the Proceedings of 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) , 2016, pp. iii.

International Conferences

• C. Bolchini, L. Cassano, A. Mazzeo, A. MIELE: Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs. In Proc. of International Symposium on On-Line Testing and Robust System Design (IOLTS), 2020, to appear.


• M.H. Haghbayan, A. MIELE, Z. Zou, H. Tenhunen, J. Plosila: Thermal-Cycling-aware Dynamic Reliability Management in Many-Core System-on-Chip. In Proc. of International Conference on Design, Automation and Testing in Europe (DATE), 2020, Grenoble, France, 2020, pp. 1229-1235.


• M. Biasielli, L. Cassano, A. MIELE: An Approximation-based Fault Detection Scheme for Image Processing Applications. In Proc. of International Conference on Design, Automation and Testing in Europe (DATE), 2020, Grenoble, France, 2020, pp. 1331-1334.


• M. Biasielli, C. Bolchini, L. Cassano, A. MIELE: A Smart Fault Detection Scheme for Reliable Image Processing Applications. In Proc. of International Conference on Design, Automation and Testing in Europe (DATE), Florence, Italy, 2019, pp. 697-703.


• D. Angioletti, F. Bertani, C. Bolchini, F. Cerizzi, A. MIELE: A Runtime Resource Management Policy for OpenCL Workloads on Heterogeneous Multicores. In Proc. of International Conference on Design, Automation and Testing in Europe (DATE), Florence, Italy, 2019, pp. 1372-1377.


• C.M. Betemps, M.S. de Melo, A.M. Rahmani, A. MIELE, N. Dutt, B. Zatt: Exploring Heterogeneous Task-Level Parallelism in a BMA Video Coding Application using System-Level Simulation. In Proc. Brazilian Symp.on Computing Systems Engineering (SBESC), Salvador, Bahia, Brazil, 2018, 75-82.


• K. Moazzemi, A. Kanduri, D. Juhasz, A. Miele, A.M. Rahmani, P. Liljeberg, A. Jantsch, N.D. Dutt: Trends in On-chip Dynamic Resource Management,'' \emph{Proc. IEEE Int. Symp. on Digital Systems Design. In Proc. of IEEE International Symposium on Digital Systems Design (DSD), Prague, Czech Republic, 2018, pp. 62-69.


• A. Kanduri, A. MIELE, A.M. Rahmani, P. Liljeberg, C. Bolchini, N.D. Dutt: Approximation-aware coordinated power/performance management for heterogeneous multi-cores. In Proc. Design Automation Conf. (DAC), San Francisco, CA, USA, 2018, pp. 68:1-68:6.


• R. Pinciroli, A. Bobbio, C. Bolchini, D. Cerotti, M. Gribaudo, A. MIELE, K. Trivedi: Epistemic Uncertainty Propagation in a Weibull Environment for a Two-Core System-on-Chip. In Proc. Int. Conf. on System Reliability and Safety (ICSRS), Milan, Italy, 2017, pp. 516-520.


• A. Bobbio, C. Bolchini, D. Cerotti, M. Gribaudo, A. MIELE: Scalable analytical model of the reliability of multi-core systems-on-chip by interacting Markovian agents. In Proc. of EAI Int. Conf. on Performance Evaluation Methodologies and Tools (VALUETOOLS), Venice, Italy, 2017, pp. 1-9.


• C. Bolchini, A. Baldassari, A. MIELE: A Dynamic Reliability Management Framework for Heterogeneous Multicore Systems. In Proc. of IEEE International Symposium on Defect and Fault-Tolerance in VLSI and Nanotechnology Systems (DFT), Cambridge, United Kingdom, 2017, pp. 68-73.


• M. Rabozzi, G. Natale, B. Festa, A.MIELE, M.D. Santambrogio: Optimizing Streaming Stencil Time-step Designs via FPGA Floorplanning. In Proc. of International Conference on Field Programmable Logic and Applications (FPL), Gent, Belgium, 2017, pp. 1-4.


• M. Pogliani, G.C. Durelli, A. MIELE, T. Becker, P. Sanders, M.D. Santambrogio and C. Bolchini: Quality of Service Driven Runtime Resource Allocation in Reconfigurable HPC Architectures. In Proc. of Conference on Embedded and Ubiquitous Computing (EUC), Paris, France, 2016, pp. 16-23.


• A. MIELE: Lifetime reliability modeling and estimation in multi-core systems. In Proc. of International VLSI Test Symposium (VTS), Las Vegas, NV, USA, 2016, pp. 1.


• M. Haghbayan, A. MIELE, A. Rahmani, J. Plosila, H. Tenhunen: A Lifetime-Aware Runtime Mapping Approach for Many-core Systems in the Dark Silicon Era. In Proc. of International Conference on Design, Automation and Testing in Europe (DATE), Dresden, Germany, 2016, pp. 854-857.


• C. Bolchini, L. Cassano , A. MIELE: Lifetime-aware Load Distribution Policies in Multi-core Systems: An In-depth Analysis. In Proc. of International Conference on Design, Automation and Testing in Europe (DATE), Dresden, Germany, 2016, pp. 804-809.


• E. Del Sozzo, G.C. Durelli, E.M.G. Trainiti, A. MIELE, M.D. Santambrogio, C. Bolchini: Workload-aware Power Optimization Strategy for Asymmetric Multiprocessors. In Proc. of International Conference on Design, Automation and Testing in Europe (DATE), Dresden, Germany, 2016, pp. 531-534.


• E.M.G. Trainiti, G.C. Durelli, A. MIELE, C. Bolchini, M.D. Santambrogio: A Self-Adaptive Approach to Efficiently Manage Energy and Performance in Tomorrow's Heterogeneous Computing Systems. In Proc. of International Conference on Design, Automation and Testing in Europe (DATE), Dresden, Germany, 2016, pp. 906-911.


• C. Bolchini, G.C. Durelli, A. MIELE, G. Pallotta, M.D. Santambrogio: An orchestrated approach to efficiently manage resources in heterogeneous system architectures. In Proc. of IEEE International Conference on Computer Design (ICCD), New York, NY, USA, 2015, pp. 221-228.


• A. MIELE, G.C. Durelli, M.D. Santambrogio, C. Bolchini: A System-Level Simulation Framework for Evaluating Resource Management Policies for Heterogeneous System Architectures. In Proc. of IEEE International Symposium on Digital Systems Design (DSD), Funchal, Portugal, 2015, pp. 637-644.


• M. Rabozzi, A. MIELE, M.D. Santambrogio: Floorplanning for Partially-Reconfigurable FPGAs via Feasible Placements Detection. In Proc. of EEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Vancouver, British Columbia, Canada, 2015, pp. 252-255.


• C. Bolchini, M. Carminati, M. Gribaudo, A. MIELE: A lightweight and open-source framework for the lifetime estimation of multicore systems. In Proc. of IEEE International Conference on Computer Design (ICCD), Seoul, South Korea, 2014, pp. 166-172.


• M. Psarakis, A. Vavousis, C. Bolchini, A. MIELE: Design and implementation of a Self-Healing Processor on SRAM-based FPGAs. In Proc. of IEEE International Symposium on Defect and Fault-Tolerance in VLSI and Nanotechnology Systems (DFT), Amsterdam, The Netherlands, 2014, pp. 165-170.


• G.C. Durelli, M. Pogliani, A. MIELE, C. Plessl, H. Riebler, M.D. Santambrogio, G. Vaz, C. Bolchini: Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In Proc. of International Symposium on Parallel and Distributed Processing with Applications (ISPA), Milan, Italy, 2014, pp. 142-149.


• G.C. Durelli, M. Coppola, K. Djafarian, G. Kornaros, A. MIELE, M. Paolino, O. Pell, C. Plessl, M.D. Santambrogio, C. Bolchini: SAVE: Towards efficient resource management in heterogeneous system architectures. In Proc. of International Symposium on Applied Reconfigurable Computing (ARC), Vilamoura, Portugal, 2014, pp. 337-344.


• C. Bolchini, A. MIELE, A. Das, A. Kumar, B. Veeravalli: Combined DVFS and Mapping Exploration for Lifetime and Soft-Error Susceptibility Improvement in MPSoCs. In Proc. of International Conference on Design, Automation and Testing in Europe (DATE), Dresden, Germany, 2014, pp. 1-6.


• A. MIELE, E. Quintarelli, E. Rabosio, L. Tanca: ADaPT: Automatic Data Personalization Based on Contextual Preferences. In Proc. of IEEE International Conference on Data Engineering (ICDE), Chicago, IL, USA, 2014, pp. 1234-1237.


• C. Bolchini, M. Carminati, A. MIELE, A. Das, A. Kumar, B. Veeravalli: Run-Time Mapping for Reliable Many-Cores Based on Energy/Performance Trade-offs. In Proc. of IEEE International Symposium on Defect and Fault-Tolerance in VLSI and Nanotechnology Systems (DFT), New York City, NY, USA, 2013, pp. 58-64.


• C. Bolchini, M. Carminati, A. MIELE, E. Quintarelli: A Framework to Model Self-Adaptive Computing Systems. In Proc. of NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Turin, Italy, 2013, pp. 71-78.


• C. Bolchini, A. MIELE, C. Sandionigi, M. Ottavi, S. Pontarelli, A. Salsano, C. Metra, M. Omaõa, D. Rossi, M. Sonza Reorda, L. Sterpone, M. Violante, S. Gerardin, M. Bagatin, A. Paccagnella: High-reliability Fault Tolerant Digital Systems in Nanometric Technologies: Characterization and Design Methodologies. In Proc. of IEEE International Symposium on Defect and Fault-Tolerance in VLSI and Nanotechnology Systems (DFT), Austin, TX, USA, 2012, pp. 121-125.


• A. MIELE, C. Pilato, D. Sciuto: An Automated Framework for the Simulation of Mapping Solutions on Heterogeneous MPSoCs. In Proc. of International Symposium on System-on-Chip (SOC), Tampere, Finland, 2012, pp. 1-6.


• C. Bolchini, A. MIELE, C. Sandionigi: Increasing autonomous fault-tolerant FPGA-based systems' lifetime. In Proc. of IEEE European Test Symposium (ETS), Annecy, France, 2012, pp. 32-37.


• C. Bolchini, A. MIELE, D. Sciuto: An Adaptive Approach for Online Fault Management in Many-Core Architectures. In Proc. of International Conference on Design, Automation and Testing in Europe (DATE), Dresden, Germany, 2012, pp. 1429-1432.


• C. Bolchini, A. MIELE: An Application-Level Dependability Analysis framework for Embedded Systems. In Proc. of IEEE International Symposium on Defect and Fault-Tolerance in VLSI and Nanotechnology Systems (DFT), Vancouver, Canada, 2011, pp. 171-178.


• C. Bolchini, A. MIELE, C. Sandionigi: Automated Resource-aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems. In Proc. of International Conference on Field Programmable Logic and Applications (FPL), Chania, Greece, 2011, pp. 532-538.


• F. Bruschi, A. MIELE, V. Rana: On-Chip Network Resource Management Design and Validation. In Proc. of International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Samos, Greece, 2011, pp. 249-254.


• C. Bolchini, A. MIELE, C. Pilato: Combined Architecture and Hardening Techniques Exploration for Reliable Embedded System Design. In Proc. of Great Lakes Symposium on VLSI (GLSVLSI), Lausanne, Switzerland, 2011, pp. 301-306.


• C. Bolchini, A. MIELE: Reliability-Driven System-Level Synthesis of Embedded Systems. In Proc. of IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT), Kyoto, Japan, 2010, pp. 34-43, Best paper award.


• C. Bolchini, L. Fossati, D. Merodio Codinachs, A. MIELE, C. Sandionigi: A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA platforms. In Proc. of IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT), Kyoto, Japan, 2010, pp. 191-199.


• C. Bolchini, P.L. Lanzi, A. MIELE: A Multi-Objective Genetic Algorithm Framework for Design Space Exploration of Reliable FPGA-based Systems. In Proc. of IEEE Congress on Evolutionary Computation (CEC), Barcelona, Spain, 2010, pp. 419-426.


• C. Bolchini, A. MIELE, C. Sandionigi, N. Battezzati, L. Sterpone, M. Violante: An Integrated Flow for the Design of Hardened Circuits on SRAM-based FPGAs. In Proc. of IEEE European Test Symposium (ETS), Prague, Czech Republic, 2010, pp. 214-219.


• C. Bolchini, F. Castro, A. MIELE: A Fault Analysis and Classifier Framework for Reliability-aware SRAM-based FPGA Systems. In Proc. of IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT), Chicago, IL, USA, 2009, pp. 173-181.


• G. Beltrame, C. Bolchini, A. MIELE: Multi-level Fault Modeling for Transaction-level Specifications. In Proc. of Great Lakes Symposium on VLSI (GLSVLSI), Boston, MA, USA, 2009, pp. 87-92.


• A. MIELE, E. Quintarelli, L. Tanca: A Methodology for Preference-based Personalization of Contextual Data. In Proc. of International Conference on Extending Database Technology (EDBT), Saint-Petersburg, Russia, 2009, pp. 287-298.


• C. Bolchini, A. MIELE: Design Space Exploration for the Design of Reliable SRAM-Based FPGA Systems. In Proc. of IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT), Boston, MA, USA, 2008, pp. 332-340.


• C. Bolchini, A. MIELE, D. Sciuto: Fault Models and Injection Strategies in SystemC Specifications. In Proc. of IEEE Euromicro Conf. on Digital System Design (DSD), Parma, Italy, 2008, pp. 88-95.


• C. Bolchini, A. MIELE, D. Sciuto: Fault Models and Injection Strategies for a Reflective Simulation Platform. In Proc. of IEEE European Test Symposium (ETS), Verbania, Italy, 2008, Poster presentation.


• G. Beltrame, C. Bolchini, L. Fossati, A. MIELE, D. Sciuto: ReSP: A Non-Intrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration. In Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, 2008, pp. 673-678, Best paper candidate.


• G. Beltrame, C. Bolchini, L. Fossati, A. MIELE, D. Sciuto: A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip. In Proc. of IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT), Rome, Italy, 2007, pp. 132-140.


• C. Bolchini, A. MIELE, M.D. Santambrogio: TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs. In Proc. of IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT), Rome, Italy, 2007, pp. 87-95.


• M. Rebaudengo, L. Sterpone, M. Violante, C. Bolchini, A. MIELE, D. Sciuto: Combined Software and Hardware Techniques for the Design of Reliable IP Processors. In Proc. of IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT), Arlington, VA, USA, 2006, pp. 265-273.


• C. Bolchini, A. MIELE, F. Salice, D. Sciuto: A Model of Soft Error Effects in Generic IP Processors. In Proc. of IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT), Monterey, CA, USA, 2005, pp. 334-342.


• C. Bolchini, A. MIELE, F. Salice, D. Sciuto, L. Pomante: Reliable System Co-Design: The FIR Case Study. In Proc. of IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT), Cannes, France, 2004, pp. 433-441.

International Workshops

• C. Bolchini, S. Cherubin, G.C. Durelli, S. Libutti, A. MIELE, M.D. Santambrogio: A Runtime Controller for OpenCL Applications on Heterogeneous System Architectures. In Proc. Embedded Operating Systems Workshop (EWiLi), Pittsburgh, PA, USA, 2016, pp. 1-6.


• E. Del Sozzo, A. Solazzo, A. MIELE, M.D. Santambrogio: On the Automation of High Level Synthesis of Convolutional Neural Networks. In Proc. Reconfigurable Architecture Workshop (RAW), Chicago, IL, USA, 2016, pp. 217-224, Best demo award.


• C. Bolchini, M. Carminati, A. MIELE: Towards the Design of Tunable Dependable Systems. In Proc. of Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN), Annecy, France, 2012, pp. 17-21.


• L. Baresi, C. Ghezzi, A. MIELE, M. Miraz, A. Naggi, Filippo Pacifici: Hybrid Service Oriented Architectures: a Case-Study in the Automotive Domain. In Proc. of International Workshop on Software Engineering and Middleware (SEM), Lisbon, Portugal, 2005, pp. 62-68.

National Conferences

• C. Bolchini, C. Curino, M. Giorgetta, A. Giusti, A. MIELE, F. A. Schreiber, L. Tanca: PoLiDBMS: Design and Prototype Implementation of a DBMS for Portable Devices. In Proc. on 12th Italian Symposium on Advanced Database Systems (SEBD), Pula, Italy, 2004, pp. 166-177.

Design and analysis of reliable computing systems

Reliability aspects play a relevant role in computing systems' design, not only in mission-critical application scenarios as traditionally occurred, but also in more common environments, due to their pervasiveness in today's life. Moreover, the susceptibility of digital systems to faults, both transient ones mainly caused by environmental phenomena (such as radiations) and permanent ones due to aging and wear-out effects, has increased due to the aggressive technological scaling. Being the problem not new, although becoming more and more relevant, literature offers a wide set of reliability-oriented design techniques, devoted to the introduction of fault detection or tolerance properties in the system. However, the common practice of considering the system hardening step and the reliability analysis separately from the main design flow (as typically done in the embedded systems' design scenario) does not suffice, because of the many issues the designer has to face with (e.g. increasing system complexity, stringent time-to-market and cost requirements).
The goal of Dr. Miele's research is the study of new methodologies for the design and the analysis of computing systems with reliability requirements. These methodologies need to be able to deal with system reliability issues right from the beginning of the design flow, and to include them as part of the overall process with a holistic approach; in this way, it is possible to drive the several decisions by exploiting the synergy of both classical aspects and reliability-oriented ones. In these years, different architectures and technological platforms have been considered (from traditional embedded systems to reconfigurable FPGA-based systems and heterogeneous multi-core and many-core system architectures), proposing hardening methodologies and tools enabling the system to autonomously detect the occurrence of a fault and possibly mask/mitigate its effects. In the recent years, this interest has evolved towards i) the design of self-adaptive reliable systems, able to dynamically adapt to the occurrence of faults, also considering the varying conditions of the working environment, and ii) to the handling of device wear-out issues, that can be effectively mitigated by means of suitable workload distribution strategies in order to balance the aging trend of the various processing resources.

2019 - 2020

• Informatica - Lecturer
  
• Reti Logiche - Lecturer
  
• Reti Logiche - Teaching assistant
  Prof. Gianluca Palermo
  

2018 - 2019

• Advanced Topics on Reconfigurable FPGA-based Systems Design - Lecturer with Dr. Marco Santambrogio.
  
• Informatica - Lecturer
  
• Reti Logiche - Lecturer
  
• Reti Logiche - Teaching assistant
  Prof. Gianluca Palermo
  

2017 - 2018

• Advanced Topics on Heterogeneous System Architectures - Lecturer with Dr. Marco Santambrogio.
  
• Informatica - Lecturer
  
• Reti Logiche - Teaching assistant
  Prof. Gianluca Palermo
  

2016 - 2017

• Advanced Topics on Reconfigurable FPGA-based Systems Design - Lecturer with Dr. Marco Santambrogio.
  
• Informatica - Lecturer
  
• Reti Logiche - Teaching assistant
  Prof. Gianluca Palermo
  

2015 - 2016

• Heterogeneous System Architectures - Lecturer
  at University of Turku (Finland)
  
• Advanced Topics on Heterogeneous System Architectures - Lecturer with Dr. Marco Santambrogio.
  
• Informatica B - Lecturer
  
• Reti Logiche - Teaching assistant
  Prof. Gianluca Palermo
  

2014 - 2015

• Informatica B - Lecturer
  
• Reti Logiche - Teaching assistant
  Prof. Cristiana Bolchini
  

2013 - 2014

• Informatica B - Contract professor
  
• Reti Logiche - Teaching assistant
  Prof. Cristiana Bolchini
  

2012 - 2013

• Informatica (per Aerospaziali) - Teaching assistant
  Prof. Fausto Distante
  
• Reti Logiche - Teaching assistant
  Prof. Cristiana Bolchini
  
• Fondamenti di Informatica - Teaching assistant
  Prof. Cristiana Bolchini
  
• Fondamenti di Informatica - Lab. supervisor
  Prof. Cristiana Bolchini
  

2011 - 2012

• Dependable Systems - Teaching assistant
  Prof. Cristiana Bolchini
  
• Informatica (per Aerospaziali) - Teaching assistant
  Prof. Fausto Distante
  
• Reti Logiche - Teaching assistant
  Prof. Cristiana Bolchini
  
• Fondamenti di Informatica - Lab. supervisor
  Prof. Cristiana Bolchini
  

2010 - 2011

• Informatica (per Aerospaziali) - Teaching assistant
  Prof. Fausto Distante
  
• Reti Logiche - Teaching assistant
  Prof. Cristiana Bolchini
  
• Fondamenti di Informatica - Lab. supervisor
  Prof. Cristiana Bolchini
  

2009 - 2010

• Reti Logiche - Teaching assistant
  Prof. Cristiana Bolchini
  
• Fondamenti di Informatica - Lab. supervisor
  Prof. Cristiana Bolchini
  

2007 - 2008

• Laboratorio Software - Teaching assistant
  Prof. Cristiana Bolchini
  
• Informatica B (per Ingegneria Fisica) - Teaching assistant
  Prof. Lorenzo Mezzalira
  

2006 - 2007

• Informatica B - Teaching assistant
  Prof. Fausto Distante
  
• Informatica B (per Ingegneria Fisica) - Teaching assistant
  Prof. Lorenzo Mezzalira